Sweep, staircase, and blanking
Aug 17, 2016

We’ve all seen images like this before:

Well, maybe not consciously, but this is the way images are “painted” across the screen of a CRT in old TVs. A sweep from left to right, combined with a step-wise change in the vertical direction. The dotted curves joining the straight lines are the “flyback” of the electron beam moving to the next step.

It’s also the basis of a Curve Tracer, used to plot the characteristics of semiconductors and other components: one variable is varied continuously, while another one changes in discrete steps. Do this fast enough and you get a constant “image” on an oscilloscope, when it’s set to X-Y mode.

Not to be confused with a Component Tester, which applies a sine wave and measures voltage + current patterns …

It’s very easy to generate these signals, you just need two digital output pins, each with an RC filter to smooth out some pulses.

The trick is to use a delta-sigma modulator to toggle an output pin such that the duty-cycle matches the desired analog output value. As this page shows, that can be done in an FPGA with a few lines of Verilog code:

module dac (input clk, output outx, outy, outz);

reg [31:0] count;
reg [15:0] accx;
reg [15:0] accy;

always @(posedge clk) begin
    count <= count + 1;
    accx <= accx[14:0] + count[17:3];
    accy <= accy[14:0] + { count[20:18], 12'b0 };

assign outx = accx[15];
assign outy = accy[15];
assign outz = count[17:3] >= 4096;


As an extra feature, we’re also generating a “Z-blanking” signal which suppresses the beam display in the oscilloscope during the flyback periods, leading to a cleaner image:

Here are the same three generated signals, using the normal Y-T scope display mode:

You can see the sweeps (yellow), the steps (blue), and the flyback suppress (magenta) signals. The cycle time is about 24 Hz when driven from a 50 MHz input clock.

Here is my setup to generate these signals:

On the bottom left is a small custom board attached to the PMOD connector, with two 10 KHz low-pass RC filters (1 kΩ + 0.1 µF).

Only 3 I/O pins and 48 LEs (under 1% of the FPGA resources) are used in this setup.

I find these “crossovers” between analog vs. digital and FPGAs vs. µCs fascinating!

For comments, visit the forum.

VGA in Verilog
Aug 10, 2016

Verilog is a Hardware Description Language - you can “write” logic circuits in it. It’s very intriguing due to its built-in parallelism and the way an actual circuit can be inferred from a high-level behavioural description.

While googling around, I found a very simple VGA video signal generator in Verilog on the TinyVGA.com website. This generates an analog VGA signal with the help of a few resistors, which can be viewed on any VGA monitor supporting the industry-standard 640x480 layout.

After some setup in Quartus Prime Lite and a little tweaking, we can generate a 256-colour pattern - it’s under 60 lines of code.

Here is some sample output (this one is displaying 1024x600 pixels, the native resolution of the 7” LCD unit I’m using):

Looking at the code, you can probably guess what the different lines are doing, although there are many subtle details - it’s quite confusing when coming from a sequential code mindset, where everything happens in a single thread of execution.

But this really is a different beast - which you can see from a diagram of the circuit elements, as generated (!) by the software:

(click on the image for a larger version)

The clk input on the left is 50 MHz.

As shown here, there are logic gates, latches, counters, and multiplexers involved. Which is exactly what FPGA’s are about: defining a (virtual) logic circuit in such a way that it can be mapped onto the primitive “Logic Element” circuits of a (real) CPLD or FPGA.

In this example, the circuit to generate a VGA test signal requires only 60 LE’s (68 for the 1024x600 version), i.e. less than 1% of the available LE’s in the low-end Cyclone IV chip I’m using (an EP4CE6, using that third board mentioned in last week’s post).

This logic synthesis process has been in use and refined in the FPGA world for decades. This explains the somewhat old-fashioned user experience you get from Altera’s Quartus and Xilinx’s ISE + Vivado IDEs.

Somehow I can’t help but think that there is a substantial overlap with the visual design tools I’m after for the JET project: with Flow Based Programming and Pure Data / MAX-MSP tools, you end up dragging circuit blocks around and wiring them up.

It feels more or less like the same task, even when the “signals” are messages and data packets, instead of electrical pulses…

PS. For a nice 40-page intro with many tips, see Introduction to CPLD and FPGA Design (PDF) by Bob Zeidman.

For comments, visit the forum.

Aug 3, 2016

It’s vacation time - I’m having fun doodling with logic devices and gate arrays… have been messing about with them before, when duplicating Grant Searle’s neat Z80 setup.

This time I want to write some code myself. There are zillions of FPGA boards, so here’s what I’ve narrowed it down to:

From left to right:

  • MAX II CPLD - with 240 logic elements (LEs), 1K of flash memory, and 80 I/O pins - this eBay board is $7, but you also need this $3 USB Blaster to program it

  • Cyclone IV FPGA - 6,272 LEs, 30K block RAM - $26 on eBay, again needs an external USB Blaster - board includes a serial-USB interface and 8 LEDs

  • another Cyclone IV (same 6,272 LEs and 30K BRAM) - $45 on eBay, but with USB Blaster built-in, and lots of goodies on board: 32 MB SDRAM, 7-segment LEDs, VGA, PS2, 12-bit ADC, 2 PMOD headers

  • for larger designs, there’s the DE0-Nano from Terasic ($79 + shipping) - it has a beefier Cyclone IV (22,320 LE’s w/ 66K BRAM), 32 MB SDRAM, and more

All of these need a (free-but-proprietary) toolchain, i.e. Altera’s Quartus Prime Lite. I’ve set up an Ubuntu 14.04 LTS VM, which makes it fairly easy to use, even on my Mac.

Cyclone II boards (e.g. the EP2C5 used for the Z80) can be had for $16, but these only work with the older Quartus II (v13.0sp1).

The other major supplier is Xilinx. Both of the older Spartan-3 and Spartan-6 chips need an obsolete toolchain (ISE v14.7), only big/pricey chips can use the latest release (Vivado v2016.2). Also, programming w/ ISE from Linux leads to USB-driver-hell, so I picked Altera (which is now part of Intel).

The first thing I wanted to try is a blinking LED on the CPLD, the smallest device - just to see how it works. Here’s the Verilog code:

module blink (input clk, output led);
    reg [31:0] count;
    always @(posedge clk) count <= count + 1;
    assign led = count[23];

It divides the 50 MHz clock and ties the 24th bit to an LED, which then ends up blinking at around 3 Hz. The toolchain takes some getting used to, but all I had to do was define the pins to use, and get the USB programmer working from inside the VM.

Whee - that was easy!

Let’s up the ante a bit. Here is a slightly more interesting 6-bit Gray code counter:

module blink (
        input clk,
        output led, led1, led2, led3, led4, led5, led6

    reg [31:0] count;
    always @(posedge clk) count <= count + 1;

    assign led = count[23];

    assign led1 = count[24] ^ count[25];
    assign led2 = count[25] ^ count[26];
    assign led3 = count[26] ^ count[27];
    assign led4 = count[27] ^ count[28];
    assign led5 = count[28] ^ count[29];
    assign led6 = count[29];

Very similar, but now we tie 6 more LEDs to the XORs of adjacent bits in a slightly larger counter. Gray code is a way of counting in binary, whereby each count only changes one LED at a time. This uses a mere 35 LEs.

After adjusting the chip type and I/O pins, it runs on all the boards listed above.

Here’s a 20-sec video of the code in action.

I rather like that 3rd FPGA “learning board” with all the on-board goodies. It requires a single USB cable for power + programming, and there’s plenty on there to play with!

For comments, visit the forum.

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