PMOD connectors
Aug 24, 2016

Last week’s post used the 12-pin “Pmod” connector on my FPGA board to generate the X, Y, and Z signals.

Pmod™ is a simple header pinout standard (PDF) defined by Digilent. There’s a (free) license for this, but only if we actually call it Pmod. So I won’t - I’ll simply refer to the two variants as 6-pin and 12-pin headers…

  • the 6-pin header is: IO1 IO2 IO3 IO4 GND +3.3V
  • the 12-pin header adds a 2nd row with: IO5..IO8 GND +3.3V

This scheme is extremely flexible, because FPGA’s can assign any function to any IO pin, and the 12-pin variant can also be used as two independent 6-pin connections.

A few more conventions are often used for the most common interfaces:

I2C – IO1..2 = SCL SDA

Another great convention, is that multiple headers are placed 0.3” apart, so that modules which need more than 8 I/O pins can simply have multiple headers placed next to each other for 16, 24, or even 32 bits of I/O goodness.

So here’s a custom module, with 3 D/A “converters” in the form of 1 kΩ + 0.1 µF RC filters, plus one digital I/O pass-through:

This in turn forms the input for an op-amp used as amplifier, level-shifter, and buffer:

The circuit on the above board is as follows:

There is room to include a dual-voltage DC-DC boost regulator, but for now I’m just feeding it ±10V from my lab power supply:

(PS. What a Kabelsalat / wire mess …)

Note that the third DAC output is used as a fixed reference for the two opamps, to allow shifting their output levels to a more or less symmetric swing around zero:

These connectors are really convenient!

There are commercial Pmod modules, but it’s just as easy to create custom ones using this same pinout. So much so in fact, that I’ve created a little 40-pin-to-quad-12-pin header breakout board for it:

From left to right:

  • the hand-wired breakout board
  • an EP4CE6 “Mini” from eBay
  • an EP4CE22 DE0-Nano from Terasic
  • an XC6SLX9 “Mini” from eBay

These all have 2 compatible 2x20 headers.

Here are some more ideas for plugs:

  • serial I/O using an FTDI adapter
  • very cheap µSD card “adapter”
  • I2C or SPI: flash/SRAM/FRAM
  • PS2 keyboard + VGA (8-colours)

The last two of these haven’t been wired up yet, but you get the idea…

For comments, visit the forum.

Sweep, staircase, and blanking
Aug 17, 2016

We’ve all seen images like this before:

Well, maybe not consciously, but this is the way images are “painted” across the screen of a CRT in old TVs. A sweep from left to right, combined with a step-wise change in the vertical direction. The dotted curves joining the straight lines are the “flyback” of the electron beam moving to the next step.

It’s also the basis of a Curve Tracer, used to plot the characteristics of semiconductors and other components: one variable is varied continuously, while another one changes in discrete steps. Do this fast enough and you get a constant “image” on an oscilloscope, when it’s set to X-Y mode.

Not to be confused with a Component Tester, which applies a sine wave and measures voltage + current patterns …

It’s very easy to generate these signals, you just need two digital output pins, each with an RC filter to smooth out some pulses.

The trick is to use a delta-sigma modulator to toggle an output pin such that the duty-cycle matches the desired analog output value. As this page shows, that can be done in an FPGA with a few lines of Verilog code:

module dac (input clk, output outx, outy, outz);

reg [31:0] count;
reg [15:0] accx;
reg [15:0] accy;

always @(posedge clk) begin
    count <= count + 1;
    accx <= accx[14:0] + count[17:3];
    accy <= accy[14:0] + { count[20:18], 12'b0 };

assign outx = accx[15];
assign outy = accy[15];
assign outz = count[17:3] >= 4096;


As an extra feature, we’re also generating a “Z-blanking” signal which suppresses the beam display in the oscilloscope during the flyback periods, leading to a cleaner image:

Here are the same three generated signals, using the normal Y-T scope display mode:

You can see the sweeps (yellow), the steps (blue), and the flyback suppress (magenta) signals. The cycle time is about 24 Hz when driven from a 50 MHz input clock.

Here is my setup to generate these signals:

On the bottom left is a small custom board attached to the PMOD connector, with two 10 KHz low-pass RC filters (1 kΩ + 0.1 µF).

Only 3 I/O pins and 48 LEs (under 1% of the FPGA resources) are used in this setup.

I find these “crossovers” between analog vs. digital and FPGAs vs. µCs fascinating!

For comments, visit the forum.

VGA in Verilog
Aug 10, 2016

Verilog is a Hardware Description Language - you can “write” logic circuits in it. It’s very intriguing due to its built-in parallelism and the way an actual circuit can be inferred from a high-level behavioural description.

While googling around, I found a very simple VGA video signal generator in Verilog on the website. This generates an analog VGA signal with the help of a few resistors, which can be viewed on any VGA monitor supporting the industry-standard 640x480 layout.

After some setup in Quartus Prime Lite and a little tweaking, we can generate a 256-colour pattern - it’s under 60 lines of code.

Here is some sample output (this one is displaying 1024x600 pixels, the native resolution of the 7” LCD unit I’m using):

Looking at the code, you can probably guess what the different lines are doing, although there are many subtle details - it’s quite confusing when coming from a sequential code mindset, where everything happens in a single thread of execution.

But this really is a different beast - which you can see from a diagram of the circuit elements, as generated (!) by the software:

(click on the image for a larger version)

The clk input on the left is 50 MHz.

As shown here, there are logic gates, latches, counters, and multiplexers involved. Which is exactly what FPGA’s are about: defining a (virtual) logic circuit in such a way that it can be mapped onto the primitive “Logic Element” circuits of a (real) CPLD or FPGA.

In this example, the circuit to generate a VGA test signal requires only 60 LE’s (68 for the 1024x600 version), i.e. less than 1% of the available LE’s in the low-end Cyclone IV chip I’m using (an EP4CE6, using that third board mentioned in last week’s post).

This logic synthesis process has been in use and refined in the FPGA world for decades. This explains the somewhat old-fashioned user experience you get from Altera’s Quartus and Xilinx’s ISE + Vivado IDEs.

Somehow I can’t help but think that there is a substantial overlap with the visual design tools I’m after for the JET project: with Flow Based Programming and Pure Data / MAX-MSP tools, you end up dragging circuit blocks around and wiring them up.

It feels more or less like the same task, even when the “signals” are messages and data packets, instead of electrical pulses…

PS. For a nice 40-page intro with many tips, see Introduction to CPLD and FPGA Design (PDF) by Bob Zeidman.

For comments, visit the forum.

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