Computing stuff tied to the physical world

Zero-power battery measurement

In Hardware on May 17, 2013 at 00:01

As promised, here’s a circuit which can be used to measure a voltage higher than VCC without drawing any current while not measuring:

Screen Shot 2013-05-15 at 13.40.54

Besides the fact that this needs an N-FET + I/O pin, there are several finicky details.

First of all, note that the following circuit will not drop the power consumption to zero:

Screen Shot 2013-05-15 at 14.38.42

The idea in itself is great: set DIO to logic “0″ before performing a measurement, acting as GND level for the resistor divider (10 + 10 kΩ would be fine here). Then, to switch it off, set DIO to an input, so that the pin becomes high-impedance.

The problem is that the pin divider is still connected and that the AIO pin cannot float any higher than VCC + 0.6 (the drop over the internal ESD protection diode). The top resistor remains connected between PWR and VCC + 0.6, therefore it’s still leaking some current.

That also explains why the first circuit does better: the MOSFET disconnects all I/O pins from that PWR line, so that there is just a resistor from AIO to ground (which is harmless).

But there’s a catch: we need to be able to turn the N-channel MOSFET on and off, which means we need to be able to apply a voltage to its gate which is a few volts above the drain pin (the bottom one, attached to AIO). With a resistive divider of 10 + 10 kΩ on a 6V PWR line, that voltage will immediately rise to 3V, and there’s no way the DIO pin can keep the MOSFET on (it can only go up to logic “1″, i.e. 3.3V).

The solution is to use a different divider ratio: say 50 + 10 kΩ. Then, a 6V PWR level leads to a 1V level on the AIO pin, i.e. on the drain of the MOSFET. With DIO set to “1″, that means the MOSFETs gate will be 2.3V above the drain – enough to keep it turned on.

BTW, all this tinkering over the past few days has left me with a bunch a funky headers :)

DSC_4454

Anyway, to summarise the zero-power battery monitor:

  • to work with 6V PWR, use a 50 (or 47) kΩ top resistor and 10 kΩ for the bottom one
  • use an N-channel MOSFET with low turn-on voltage (called a “logic level MOSFET”)
  • to measure the voltage, set DIO to “1″
  • measure the voltage on the AIO pin, where 0..1V will correspond to 0..6V on PWR
  • to turn off the divider, set DIO to “0″

As you can see, this approach requires an active component to switch things and an extra I/O pin, but then you do end up with a circuit which can completely switch off.

For simple uses, I’d just use yesterday’s setup – sub-microamp is usually good enough!

  1. Why don’t you use a P-channel MOSFET? You’d place it between PWR and the top resistor, of course. There are types with Ugs=2V, which should work rather well.

  2. Hi,

    how about to use the internal pullup as the lower part of the voltage devider? i thought there’s also a mosfet behind it.

    Regards Nik

    • How? It’s a pull-up, not a pull-down. Even if it were, the value is not well-defined. And it still suffers from the same problem as the second circuit.

  3. “where 0..1V will correspond to 0..6V on PWR” That is the theory, of course. And for all intents and purposes it will be so, as you won’t use a voltage divider on, say, an AA or a LiPo. But if the PWR drops, so does the voltage you can use to open the MOSFET. I can imagine that the lower limit of battery voltage that can be measured through an open FET is not by far 0V, more like 3V?

    • I’d expect this to work down to perhaps 2V for VCC (and you’ll need to use the 1.1V band-gap as ADC reference). Keep in mind that this is for measuring a battery above VCC, presumably with a down-regulator to provide the VCC. By the time it drops under say 3V, that battery is most likely well below its intended charge level (LiPo, 2x lead-acid, 3x NiMh or alkaline).

  4. If your core voltage is much below 3V, you don’t need to measure anything: you don’t have enough power to transmit whatever you measured, so why bother?

    Given that there are MOSFETs (N or P channel, take your pick) which need just 2V to switch on, I don’t see the problem.

  5. @eljonco, since the divider chain is still relatively high impedance, it is fine to run the FET sub-threshold. This extends the observable range downwards since it is not important to have the Rds in milliohms, partial turn-on is adequate until you are down probably to an unhealthy battery voltage.

  6. @matthais, using an upper PFET unfortunately has a difficulty providing the turn-on drive since its source is referenced to Vbatt, higher than the available drive from an I/O pin. Since “open drain” output is not available, this takes additional components (e.g. gate through high value R to Vbatt, an NFET or similar buffer from the I/O pin).

    • Or rather: turn-off. With P-MOS, a gate voltage lower than the top pin will make it conduct. With gate drive limited to VCC and the top being higher, that will always be the case, i.e. no way to make the P-FET turn off from a DIO pin.

  7. Hmm – no way?

    Time for some circuit trickery methinks ;-)

    PFET source to Vbatt, drain to top of divider chain, gate 2.2MΩ to Vbatt and to DIO pin:

    • Tristate DIO: (Default state) FET ‘OFF’, divider chain disabled
    • Set Logic 0: FET ‘ON’, divider chain active

    Why tricky? The DIO pin is pulled above its Vcc, activating the ESD diode on that pin – but only just, a miserly 1uA or so is “lost”.

    • You’re cheating – 1 µA ≠ 0 !

      We’re splitting hairs now, but 1 µA could be 10% of the energy budget…

  8. I’m not able to try this, but it should work: How about a capacitor between the DIO pin and the PMOS gate (with a pullup to VBatt)? You don’t need to hold the device on indefinitely, just for long enough to make a measurement. Pull the DIO pin low before making the conversion, allowing just enough time for the voltage at the divider midpoint to settle, given the capacitance at the AIO pin and the divider resistance, then take the DIO tristate after the conversion. This turns the PMOS off (and also recovers most of the charge on the capacitor into the supply rail, via the ESD diode).

    • On second thoughts I think you will need to actively drive the DIO pin high, to stop excess charge accumulating on the capacitor, and to prevent problems where the battery voltage varies a lot (as from a solar cell)

  9. @Max, chapeau!

  10. Great idea – I’ll try it out tomorrow.

  11. @Matthias: point taken. Measuring (dis)charge curves of a low drop regulator with supercap and solar 5V would be the only setup where this comes into play.

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