As promised in the previous post, here’s an improved design for controlling hard disk power.
The first conclusion is that we need to switch the positive +12V line, not the ground. Ground is inter-connected between all disks, the server, and this circuit – so we shouldn’t mess with it.
Here’s one way to do a “high-side” switch:
First problem: we don’t have a voltage higher than 12V available, so the N-MOSFET can’t simply be moved to the upper power line (it needs a few volts above its source to drive it, and when conducting, that source is at 12V). A P-MOSFET solves that, because it needs a few volts below 12V to drive it into conduction.
Second problem: we can’t drive the P-MOSFET high enough (12V) to make it disconnect, when driven from an ATmega output pin (which can’t go higher than 3.3..5V). So we need a resistor to pull the gate up, and a transistor to pull the gate down. And lastly, we need a resistor to limit the current into the transistor.
Quite a few parts, expecially since this circuit needs to be repeated for each hard disk.
For reasons which will become clear tomorrow, I’d like to simplify this circuit a bit further, and get away from handling 12V power levels. This “simplification” needs a bit of explanation, unfortunately:
To see what’s going on, this trick may help: look at the VOUT pin as being a regulated 8.7V voltage. In other words: the JeeNode “ground” is at +8.7V above ground, in relation to the power supply, hard disks, and server.
This means that the JeeNode is running with a 12 – 8.7 = 3.3V voltage difference between its 3.3V and GND pins, just as it always does. It’s merely floating a bit above ground, but that’s all relative anyway. As far as the JeeNode goes, it’s getting exactly the right power levels.
The result is that the output pins of that JeeNode will be at about 8.7V when “0” and at 12V when “1”. Which is just right to drive the gate of a suitable P-MOSFET (a “1” will turn it off, and a “0” will make it conduct).
So instead of making all the disk ground levels float, this setup places the JeeNode at an unusual 8.7V above ground level, which lets it turn on and off P-MOSFETs by controlling the positive supply line.
Now we need a regulated 8.7V supply. Eh, actually, no… we need a supply which is exactly 3.3V below the +12V line. That way, even if it fluctuates a bit from hard disk load changes, the JeeNode still gets a nice clean 3.3V.
The way to do that is to use a minus 3.3V regulator, such as an LM337. And from the perspective of that regulator, +12V is “ground” and ground is… -12V!
Perfect. You just have to look at voltages upside-down :)
Although you do have to remember never to connect a serial port to the JeeNode, unless you have a floating computer (laptop on battery power) or optoisolated com port. But I guess wired connection isn’t required anymore, if you can upload new programs via RF ?
Yep, that’s a very tricky detail. Disconnect everything (especially grounds) when programming via FTDI. RF over-the-air programming is probably still a while off (I’m working on it, but there are lots of details to get it to work and make it practical).
Seems like you’re going out of your way to design-in a posible single-point of failure — this new power subsystem. Rather than think of multiple power supplies as ‘clutter’, why not view them as ‘redundancy’ instead?
Ah, but wait: it’s not redundancy, since there is no fail-over. With N supplies there is an ≈ N times higher chance of one of them failing (my guess would be: 1-(1-p)^N, with p the failure probability).
Note that I’m not planning to use this for disks and devices which are mostly on, but for units which are off-line most of the time. A failure will bring down the 1 or 2 devices currently in use.
I agree that it’s all a bit hard to predict. Would one high-quality power supply improve the system, over whatever power plugs happen to come with the external drives?
For now, I’m still tempted to go ahead with this experiment…
I understand that you took a different approach with good reasons, so just for completeness: The transistor in the 1st circuit isn’t really needed as you could just connect the MOS-FET’s gate to an AVR pin and switch it between ground for on and high impedance (output) for off. Atmel says¹ that the AVR’s internal clamping diodes can take up to 1mA, so with an additional resistor of 2k to 10k between pin and gate or a somewhat larger pullup you should be on the safe side.
¹) This is mentioned in an appnote that describes a zero-cross detection circuit by connecting mains power to an AVR input through a pair of 1M resistors.
Ah – but it might be tricky. The clamping diode still pulls the pin “down” to at most 3.3V. So no matter what you do, even with high-Z, the pin’s voltage can’t swing more than 3.3V. Since two resistors (I/O pin to gate R1 and gate to +3.3V R2) form a voltage divider, the swing on the gate will be less than 3.3V – considerably less since R1 has to be several times R2.
(I’m using the clamping trick in tomorrow’s post, but in a very different way)
Stupid me, I entirely forgot that configuring a pin as input (high-Z) doesn’t disable the clamping diodes.