Computing stuff tied to the physical world

Direct relay switching

In Hardware on Mar 16, 2013 at 00:01

There are small relays which are just weak enough to be switched directly by the ATmega’s I/O pins, even at 3.3V. I’ve been chasing and trying out these types of relays for some time, especially the latching types which only require power to switch, not to stay on.

Today, I received a very nice surprise package from @eljonco, who sent me a nice little latching relay (from eBay) which I’ve immediately mounted on a Proto Board:


Bottom side connects DIO2 + AIO2 to one side of the coil, and DIO3 + AIO3 to the other:


Why both? Because one pin drive is not strong enough to make these units switch at 3.3V:


…whereas driving them both in parallel works, resulting in a clear clicking sound and a very nasty “inductive kick-back” switching pulse across the coil on power-off:


There are horrific things going on here, electrically speaking, which I’ll look into later.

For now, let me just explain what’s going on and how this single-coil latching relay is being switched, using four I/O pins (port 2 and 3 on a JeeNode in this case):

JC's Grid, page 68

The relay core can be switched with a brief pulse, reversing the polarity to reverse the action. So we connect it to two different I/O pins and drive it as an H-bridge. When both pin levels are the same (or when the I/O pins are floating), nothing happens. By putting one pair in “0” state and the other in “1” state, current flows through the coil.

So to turn the relay on, the actions are:

  • set DIO2 = AIO2 = 0
  • set DIO3 = AIO3 = 1
  • wait 3 ms
  • set DIO3 = AIO3 = 0 (same as DIO2 and AIO3), or make them float, i.e. inputs

To turn it off, we simply exchange the 0’s and 1’s in the above.

More on this tomorrow. Stay tuned…

  1. Do bad things happen if DIO₂ and AIO₂ go to different output states, or are the analog pins robust enough/low enough current to withstand this?

  2. Correct, mismatched states are potentially destructive. But here (a bit hidden behind that pseudo code) the control register is loaded up with the changes as a single operation. Down at chip level, the new pin status is a parallel load across all (enabled) DI/O pins on the edge of the same system I/O clock pulse – the state set operation is safe.

    I’m not so sure about those back EMF spikes though – perhaps more is revealed tomorrow.

  3. Have you considered using 2 pins on the drive side instead of the sync side? put a capacitor (and resistor if needed) inline

    2-JN-pins –/\/\/\/—eeee—||—->gnd

    Where /\/\ is a resistor, eeee is the latching relay coil, || is a capaictor

    With a latching relay you can drive the line high forever, and take no current (capacitor will charge up), and when ready to switch off, pull it low and the capacitor will source all the current needed to switch it off. The resistor is there to limit current, and can be omitted if not needed.

    • Good idea, I’ll look into it. The resistor is probably not needed, max current is probably what is needed here – given that the drive voltage is only 3.3V.

  4. Is that a real NEC relay or a copy? I’m not sure the markings on the top are right.

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