Sweep, staircase, and blanking Aug 17, 2016

We’ve all seen images like this before:

Well, maybe not consciously, but this is the way images are “painted” across the screen of a CRT in old TVs. A sweep from left to right, combined with a step-wise change in the vertical direction. The dotted curves joining the straight lines are the “flyback” of the electron beam moving to the next step.

It’s also the basis of a Curve Tracer, used to plot the characteristics of semiconductors and other components: one variable is varied continuously, while another one changes in discrete steps. Do this fast enough and you get a constant “image” on an oscilloscope, when it’s set to X-Y mode.

Not to be confused with a Component Tester, which applies a sine wave and measures voltage + current patterns …

It’s very easy to generate these signals, you just need two digital output pins, each with an RC filter to smooth out some pulses.

The trick is to use a delta-sigma modulator to toggle an output pin such that the duty-cycle matches the desired analog output value. As this page shows, that can be done in an FPGA with a few lines of Verilog code:

module dac (input clk, output outx, outy, outz);

reg [31:0] count;
reg [15:0] accx;
reg [15:0] accy;

always @(posedge clk) begin
    count <= count + 1;
    accx <= accx[14:0] + count[17:3];
    accy <= accy[14:0] + { count[20:18], 12'b0 };

assign outx = accx[15];
assign outy = accy[15];
assign outz = count[17:3] >= 4096;


As an extra feature, we’re also generating a “Z-blanking” signal which suppresses the beam display in the oscilloscope during the flyback periods, leading to a cleaner image:

Here are the same three generated signals, using the normal Y-T scope display mode:

You can see the sweeps (yellow), the steps (blue), and the flyback suppress (magenta) signals. The cycle time is about 24 Hz when driven from a 50 MHz input clock.

Here is my setup to generate these signals:

On the bottom left is a small custom board attached to the PMOD connector, with two 10 KHz low-pass RC filters (1 kΩ + 0.1 µF).

Only 3 I/O pins and 48 LEs (under 1% of the FPGA resources) are used in this setup.

I find these “crossovers” between analog vs. digital and FPGAs vs. µCs fascinating!

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