VGA in Verilog Aug 10, 2016
Verilog is a Hardware Description Language - you can “write” logic circuits in it. It’s very intriguing due to its built-in parallelism and the way an actual circuit can be inferred from a high-level behavioural description.
While googling around, I found a very simple VGA video signal generator in Verilog on the TinyVGA.com website. This generates an analog VGA signal with the help of a few resistors, which can be viewed on any VGA monitor supporting the industry-standard 640x480 layout.
After some setup in Quartus Prime Lite and a little tweaking, we can generate a 256-colour pattern - it’s under 60 lines of code.
Here is some sample output (this one is displaying 1024x600 pixels, the native resolution of the 7” LCD unit I’m using):
Looking at the code, you can probably guess what the different lines are doing, although there are many subtle details - it’s quite confusing when coming from a sequential code mindset, where everything happens in a single thread of execution.
But this really is a different beast - which you can see from a diagram of the circuit elements, as generated (!) by the software:
(click on the image for a larger version)
clk input on the left is 50 MHz.
As shown here, there are logic gates, latches, counters, and multiplexers involved. Which is exactly what FPGA’s are about: defining a (virtual) logic circuit in such a way that it can be mapped onto the primitive “Logic Element” circuits of a (real) CPLD or FPGA.
In this example, the circuit to generate a VGA test signal requires only 60 LE’s (68 for the 1024x600 version), i.e. less than 1% of the available LE’s in the low-end Cyclone IV chip I’m using (an EP4CE6, using that third board mentioned in last week’s post).
This logic synthesis process has been in use and refined in the FPGA world for decades. This explains the somewhat old-fashioned user experience you get from Altera’s Quartus and Xilinx’s ISE + Vivado IDEs.
Somehow I can’t help but think that there is a substantial overlap with the visual design tools I’m after for the JET project: with Flow Based Programming and Pure Data / MAX-MSP tools, you end up dragging circuit blocks around and wiring them up.
It feels more or less like the same task, even when the “signals” are messages and data packets, instead of electrical pulses…
PS. For a nice 40-page intro with many tips, see Introduction to CPLD and FPGA Design (PDF) by Bob Zeidman.