Better speed and sensitivity Apr 2016

First off, let’s find out how that last single op-amp circuit works in practice. The chip used is an LMC6484 quad CMOS op-amp with extremely high input impedance. Since it’s also rail-to-rail on both inputs and outputs, the Vs+ positive supply can be 5V and the negative Vs- supply can be -5V, as generated by the TC7660S negative voltage generator (it’s a small DIP-8 package which only needs two 10 µF capacitors to work). For reference, here is the schematic again:

Here is the above circuit on a 4x6 cm prototype board, again plugged into the RF Node Watcher:

All the resistors used are metal film and accurate to 1%. Using a lab supply, we can measure the actual voltages presented to the ADC over the full ± 25V design range - here are the results:

Vin Vadc
-25 0.065 V
-24 0.128 V
-21 0.316 V
-18 0.504 V
-15 0.692 V
-12 0.880 V
-9 1.068 V
-6 1.256 V
-3 1.444 V
0 1.633 V
3 1.821 V
6 2.009 V
9 2.197 V
12 2.386 V
15 2.574 V
18 2.762 V
21 2.950 V
24 3.138 V
25 3.201 V

As you can see, it’s all mapped inside the 0 .. 3.3V range needed for the ADC. There is a small offset: an ideal op-amp would have placed 0V at 1.650 V on the ADC, i.e. 17 mV higher than measured - this is probably due to the op-amp’s input offset plus bias current imperfections.

That same table, but now plotted to show (at least coarsely) the linearity of it all - which is not really surprising since the op-amp is being used well inside its datasheet specs:

The frequency response is flat from DC until at least 10 KHz, but there are some details to deal with w.r.t. higher frequencies - the slew rate is around 0.5 V/µs, somewhat lower than the specs in the datasheet indicate. Still, more than enough all the way into the audio frequency range.

Now, since the LMC6484 is a quad op-amp, that leaves us with 3 unused op-amps…

One option would be to add up to three more identical channels, so that this circuit could be used to measure and report/display up to 4 signals at the same time.

More interesting would be to measure lower voltage ranges with decent resolution. One use for this, is to read small voltages across a “shunt” resistor, for performing current measurements.

There are many ways to implement this sort of “auto-ranging” functionality - it comes down to where to adjust the amplification of the op-amps (or where to place switchable voltage dividers). It’s quite involved to do this on the input side, because of the dual voltage supplies.

A much simpler (albeit less precise) option, is to add an extra op-amp after the front end. Then, we don’t have to worry so much about input impedances, for example. In fact, let’s go ahead and add a cascade of 2 op-amps after the input stage:

Some notes about this circuit (which has not yet been tried, by the way):

This means that only as long as the signal stays within that small ±0.027V range, will all three ADC outputs be useful - though ADC2 sees a tiny value, ADC4 can report the 121x amplified value in nearly full 12-bit resolution, i.e. in steps which are only a fraction of a millivolt.

There is a drawback with this approach: for higher input voltages, the cascaded op-amp outputs will be “saturated” because they can’t reach high enough voltages. The output of an op-amp can never go above its V+ or below its V- supply rail, which in this case will be around+5V and -5V.

Another issue is the non-zero offset error, i.e. seeing 1.633V at ADC2, when it really ought to have been 1.650V. That offset error is going to be amplified first by U1C and then by U1D. We can compensate for it in software, but it will reduce the total range of these cascaded stages.

So what happens when the Vin2 input rises to +1V, for example?

Well, the output of U1B will be about 0.9V (the same as its input, since it’s a voltage follower.

The output of U1C will be “pegged” at approximately +5V, since it can’t go any higher (if it could, it would settle at 11 x 0.9V, i.e. ≈ 10V). This also means that ADC3 will see an input voltage of around 4.2V, which is outside its valid measurement range. The ADC will report this as “4095”, its maximum reading. Damage is not likely, since R14 will limit the current flowing into the ADC pin to well under a milliamp (the LMC6484 can handle ±5 mA).

Likewise, for U1D, which sees +5V at its input, and has no way to amplify that another 11 times. It too will have its output pegged at +5V, with the same effect on ADC4 as with U1C and ADC3.

In summary: for “large” input voltages, U1C and U1D will be pushed to their limit, and feed either +5V or -5V to the ADC’s 2:1 input voltage dividers, making their readings useless. But for smaller values, where U1B reports small values around zero (i.e. an ADC reading close to its 2000 middle range), the values from ADC3, and possibly also ADC4 will become meaningful.

We can now simply read out ADC2, see if it’s close to what represents 0V, and if so, read out ADC3, see again if it’s close to 0V, to finally check ADC4 for values really close to 0V.

Due to the input error and their substantial effect on the readings of ADC3 and ADC4, this circuit will need to be calibrated: once by shorting the input so it is exactly 0V, and once near both ends of the scale, i.e. ±25V on the input (or ±24V, if that’s more convenient). The 2nd calibration can be skipped if you’re ok with the 1% accuracy of the resistors used in the circuit.

If the input offset turns out to be too large to make U1D perform in a useful range, a manual offset compensation trimmer will have to be added to this circuit, to be calibrated once.

Well, that’s the theory anyway… we’ll have to try this out to see how it behaves!

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