Computing stuff tied to the physical world

Meet the LPC812

We’ve always been using the same ARM micrcontroller chip until now, i.e. the LPC810. Let’s move up to a somewhat more capable member of that chip family, the LPC812.

This chip has four times as much flash (16 KB), four times as much RAM (4 KB), and at least twice as many pins (16 to 20, depending on the package chosen).

The one we’re going to focus on is the 16-pin TSSOP package, shown here to the right of that “big” 8-pin DIP package:

DSC 4977

This version of the LPC812 also has:

  • three UARTs/USARTs with hardware flow-control, assignable to any free I/O pins
  • an I2C bus, assignable to any free I/O pins
  • two SPI buses, assignable to any free I/O pins

All these peripherals are capable of waking up the ┬ÁC from sleep or power-down mode.

This chip is still quite limited in the analog domain, with the same comparator plus 31-step ladder as its only built-in capability, exactly the same as the LPC810.

Here is a diagram of all the hardware, from NXP’s UM10601 datasheet:

Screen Shot 2015 03 24 at 23 10 08

The win is really on several fronts: the LPC810’s 4 KB flash memory was a bit small for more substantial code, and its 1 KB RAM was definitely a bit tight (despite not having to put text strings in there as well, as on ATmega’s and other AVR chips).

But most importantly, the LPC812 has 16 pins total, of which two are fixed for Vcc and GND, and four more are fixed if you want to be able to upload code via the extended FTDI BUB interface. That leaves 10 pins of goodness, and most of them are freely assignable (and re-assignable!) due to the LPC8xx’s very flexible “any-to-any” switch matrix.

One caveat: two pins (PIO0_10 and PIO0_11) have been specifically designed to be used as I2C pins, and are slightly less functional as general-purpose I/O pins. They lack pull-up circuitry. Which is fine if we use them purely for input, but they can’t turn a “1” into a high level. We can only use them as open-collector outputs, which treat a “1” as high-Z.

There’s no EEPROM on these chips, but this can be (sort of) emulated with flash memory.

As with any LPC8xx, there’s a built-in boot ROM as well as some extra callable functions – so uploading with serial / FTDI works out of the box, even if the currently loaded code is unresponsive. In the worst case when all pins have been disabled, the chip can be forced into boot mode by power-cycling it with the ISP pin pulled low (PIO0_12 on the LPC812).

The best part is that the LPC812 is really a superset of the LPC810 in terms of hardware, and just about 100% compatible in terms of what code can run on it. Even if different pins are used, our code can re-arrange their use on startup, and keep everything else the same.

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