Computing stuff tied to the physical world

Anatomy of a power-up

A chip gets power, then “comes out of reset”, and that’s it, right?

Not so fast. When it comes to ultra-low power consumption, the hard part is often dominated by what the chip does before it enters its official reset state. The MPS is an excellent example – and it matters greatly because of its extremely limited energy budget.

Many problems had to be overcome to steer all the components involved into such a direction that they actually get to that reset state, and then start doing their job. Here is a scope capture of the startup process, before entering the main processing & transmit loop:


  • the yellow line is Vres, the supply voltage over C1 + C2
  • the red trace is calculated as the derivative (i.e. slope) of the yellow line
  • the blue line is Vradio, the voltage on the RFM69’s Vcc pin

The vertical zero origin of the yellow and blue traces are just above the white “V-Marker: (CH1)” text. The derivative is centred 5 divisions from the top, and briefly goes negative. Horizontal divisions are 100 ms each, vertical is 500 mV/div for the yellow & blue traces.

This image contains all the details of the startup timeline in exquisite detail:

  • the trigger point (T=0) is one division from the left edge of the graph
  • power is turned on, the capacitors start to charge up
  • at about T+365ms, where the dotted “1” marker is, Q1 & Q2 turn on
  • Vres is 1.97V at this point, the supply to the LPC810 µC is now on
  • current starts to flow, and Vres drops for the next 44 ms
  • for some strange reason, explained below, Vradio starts to rise as well
  • at about T+410ms, marker “2”, the µC comes out of reset and starts main()
  • it configures various I/O pins, preventing a further rise of Vradio
  • at this point, we’ve now lost 0.325V of the supply voltage, Vres
  • the µC goes into power down, drawing only a few µA in this state
  • now Vres can rise further, until C1+C2 have been charged up

The derivative (red line) corresponds to the rate of change of Vres, and is therefore a good indicator of the current flowing into (and briefly out of) the reservoir capacitors.

Why is Vradio rising?

From everything described about the Micro Power Snitch until now, it should be clear that the power up sequence is very carefully controlled by all the components in the circuit. This sequence defines that T+365ms point where the LPC810 is switched on. Meanwhile, the radio supply voltage will remain off, since power to it is controlled by its own MOSFET (Q3), which is tied to an I/O pin. And R9 is set up to keep the MOSFET “open”, initially.

So why is the blue trace rising at all, given that the radio’s power is turned on much later?

The reason is that current can flow through a chip in very unexpected ways when it is not powered up. In this case, the SPI I/O pins on the RFM69 module are the culprit, through a mechanism which could be called “back-feeding”.

It can severely mess up a power-up sequence when not all parts of the circuit are powered at the same time. As in the MPS, which wants to keep the radio off for various reasons.

We need to understand why and how the radio is mis-behaving, and what to do about it.

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