Computing stuff tied to the physical world

Frequency generator

In Hardware on Jan 11, 2012 at 00:01

A long time ago, I got this DDS-60 kit, which is a small circuit based on an AD9851 DDS chip:

It has everything on board to generate a sine wave from 0..30 MHz, and my intention was to hook it up to a JeeNode (as part of a long term plan of mine to set up a more extensive wirelessly-controlled electronics lab):

Never got it to work at the time, but now with the new scope, there really is no excuse anymore. First check, as indicated in their build instructions, is to verify that the crystal oscillator is feeding a 30 MHz clock into the chip:

Looking good. Very impressive rise and fall times, BTW.

When driven at 30 MHz, the AD9851 output frequency is settable in steps of 0.006984919 Hz. In other words, a multiplier of 1000 will generate a sine wave of ≈ 7 Hz.

Here’s the output when programmed to generate 10 MHz (multiplier 1431655765, i.e. 9999999.9977 Hz):

Whoa… it’s 10 MHz, but a far cry from a sine wave. Ah, but that’s not really surprising: this thing uses DDS to synthesize a sine wave, as recently described on this weblog. With 30 MHz sample rate, i.e. 3 samples per wave, it’s not really possible to create a decent 10 MHz sine wave (not even a symmetrical shape in fact, as you can see).

But the AD9851 has a trick up its sleeve: it includes a “6x” multiplier option, which causes it to internally generate a reference frequency which is 6x the incoming clock, i.e. 180 MHz in this case.

Using that, and adjusting the frequency setting to work at 180 MSa/sec, we get a much better approximation:

Still not perfect, but by analyzing the FFT of this signal, we can find out what’s going on:

This output signal is made up mostly of a 10 MHz sine, with another peak at 90 MHz.

Unfortunately, the output circuit on this board isn’t working yet (this is what probably threw me off when trying this circuit before), so I can’t test the effect of the 60 MHz low-pass filter yet. It won’t filter out the 30 MHz residue visible in that last picture, but should definitely reduce the frequency components over 60 MHz.

Ok, all the important bits seem to work – I “only” need to troubleshoot that analog back end a bit more.

Update – I found the problem: the SMD trimpot was fractured, i.e. no contact. I’ve replaced it with a fixed 220 Ω resistor for now – this brings the output to ≈ 680 mVpp (or 350 mVpp into 50 Ω) – the sine wave output is now considerably cleaner, but several of the frequency peaks ≥ 90 MHz are still present:

I suspect that the 30 MHz clock is “feeding through” somewhere, perhaps better decoupling would avoid that.

1. If you can tweak the output level to 0.5v pk-pk, then it matches the reference level 7dbM (5mW output) – allowing conversion of the FFT output to absolute rather than relative measures. If the buffer/filter is well designed, its output may be essentially flat in the passband.

A good reference to the various db measures is [here] (http://designtools.analog.com/dt/dbconvert/dbconvert.html “”)

2. Interesting spikes in the output spectrum. Note that since DDS is a sampling system, our friend Mr. Nyquist comes into the picture. The output contains “folded” harmonics of the form Fclk – n*Foutput, with odd n stronger than even. In this case 180-n*10Mhz i.e. 170,160,150,..120..90….. The highlighted harmonics match multiples of the original clock frequency of 30Mhz, algebraically adding to any of its harmonics leaking into the output.

Choosing a mutually prime Foutput would separate out the aliasing from clock harmonic spikes in the FFT.

That 1431655765 multiplier looked strangely familiar – of course, 0101…..0101

3. You are a mine of very useful info Mr J :-)

4. A mine is apt perhaps – have to dig deep to find the nuggets amongst the accumulated dross ! ;-)