If low-side switching is so troublesome, then why not just flip everything around, right?
Not so fast. The I/O pin is tied to a microcontroller running at 3.3 or 5V, so its voltage level will vary between 0 and a few volts. Whereas “+” is more likely to be 5V, 12V, or even 24V.
This means that to keep the PNP transistor switched off, we need to keep the base voltage at nearly the same level as that “+” line. Unfortunately, this is impossible – not only could high voltages on I/O pins of a µC damage them, there is also some protection circuitry on each pin to protect against electrostatic discharge (ESD). If you were to look inside the µC chip, you’d find something like this on each I/O pin:
What that means is that if you try to pull an I/O pin up to over VCC+0.7V, then that topmost diode will start to conduct. This is no problem as long as the current stays under 1 mA or so, but it does mean that the actual voltage of an I/O pin will never be more than 4V (when running on 3.3V). Which means that PNP transistor shown in the first image will always be on, regardless of the I/O pin state.
We’ll need a more complex circuit to implement a practical high-side power-on switch:
The workhorse, i.e. the real switch, is still the PNP transistor on the right. But now there’s an an extra “stage” in front to isolate the I/O pin from the higher voltages on the base of that PNP transistor. There’s now essentially a low-side switch in front of the PNP.
When I/O is “0”, no current flows into the base of the NPN transistor, which means it won’t conduct, and hence no current flows into the base of the PNP transistor either.
When I/O is “1”, the NPN transistor will conduct and pull its collector towards ground. That leaves a 10 kΩ resistor between almost ground (0.4V) and almost high (“+” – 0.7V), since the base-to-emitter junction of a transistor is more or less a forward-conducting diode. So the base of the PNP transistor is pulled down, and the PNP transistor is switched on. The resistor values are not too critical here – making them both 10 kΩ would also work fine. But they have to be present to limit both base currents.
A similar circuit can be created with two MOSFETs. With the proper choice of MOSFETs, this will in fact be a better option, because it can handle more current and will have less power loss (i.e. heat). The resistors will need to be placed differently.
Note that all circuits can be analysed & explained in the same way, as long as there are no feedback loops: step-by-step, reasoning about the effect of each stage on the next.
A couple of days ago I was experimenting with a low side switch (2n3904) used to turn on a voltage divider hooked directly to battery V+ (4.5v in the final prototype). Idea was to use it as an on demand voltage monitor — turn it on, analogRead on voltage across the divider to get an idea of battery health, then turn it off until needed again. But your post on low side switching brings up two issues, if I’m interpreting it correctly — residual voltage drop across the transistor could cause the signal level to the analog pin to float, introducing innacuracies to the reading, and when switched off, with no clear route to ground, rogue trons could storm the analog pin and potentially damage it. The later probably not much of a concern at 4.5v, but if the same approach were used with 9v? Would a high side arrangement like you’ve outlined here be a better approach?
Yep.
I would advice to add another resistor from the collector of the npn transistor or the base of the pnp transistor to the high voltage side (the emitter of the pnp transistor). That way any leakage through the npn transistor will be compensated and the pnp transistor will shutdown a bit faster.
Good point. I was trying to save an extra component, but yes – leakage through the NPN can cause some residual current.
I’ve never 100% understood the high side switch schematic. So the resistor you sometimes see that pulls the NPN collector high is to compensate for leakage current in the NPN? Looking at it I thought that was to pull the PNP base high so it doesn’t float when the NPN is not conducting. Does the topology of the high side switch make that not an issue?
Re pull-up vs not-floating: that’s more or less the same thing, really. You need the PNP’s base to stay at “+” or at least not more than 0.65V below that.
Without NPN, the base of the PNP would never get any current. With the NPN, all it gets is the current leakage of the NPN. Depending on specs that might be enough to start driving the PNP into conduction. The current gain can be over 400 on an BC549 (NPN) or a BV559 (PNP). IOW, it would only take 2.5 µA of leakage in the NPN to make the PNP transistor pass 1 mA through. The NPN, in turn, needs less than 6 nA, to produce that 2.5 µA in its collector.
I’d have to measure to see whether this matters in a real circuit, but think that the pull-up suggested by Wilko might be a good idea after all – if the goal is to make the PNP transistor really switch off well.
@CapnBry, since BJT’s are essentially current driven devices, there isn’t the same issue of “floating” that is seen with a FET gate. It is easier to analyze the circuit in the current domain.
With the I/O pin “low”, Q1 base sees ground and there is a leakage current through the collector of a few uA. If the I/O pin is floating, there is a similar, possibly larger value leakage current since there is a hidden base drive of ~ +/- 1uA (See I/O pin specification). If this drive is positive, it gets reflected in the collector as ~Beta times larger.
As drawn, the only path for Ic Q1 is the base of Q2. That relects similarily in Ic Q2 multiplied up by ~Beta again. Bottom line is a quiescent current through the load in the “OFF” state.
At room temperatures and with modern silicon BJT’s the quiescent current may be small enough to be ignored for most applications (see jcw’s sample values above).
For minimal power drain and/or extended temperature range, a path is needed from Q1 collector to some +ve rail. A high value resistor works fine.
Looking at chip equivalant schematics where this topology is seen for level shifting, that resistor is often replaced by a constant current source. This has some advantages but is chosen mostly because the silicon area for a constant current source is less than that required to make a high value resistor with some foundry processes.
Alright! Now I think I understand. I wasn’t thinking about the fact that the teeny leakage current would be multiplied by the beta of the transistor multiplied by the beta of the other transistor. I’ve also learned that I/O pins aren’t perfect and have some current flow when “off”, so this has been educational all around. Thanks guys!