Computing stuff tied to the physical world

It’s no longer a capacitor!

In Hardware on Mar 10, 2013 at 00:01

Yesterday’s post was about plotting the response of a decoupling capacitor versus frequency. It might not seem like much, but this is in effect exactly what a Spectrum Analyser with “Tracking Generator” does! You put a signal with a known frequency and amplitude into a circuit, and you look at the amplitude of the signal that comes out. As you saw, these plots give instant insight in what an analog circuit is doing to signals. And if we were to somehow also measure the phase shift of the signal, we’d in fact have a Vector Network Analyser – an instrument which usually costs more than an average car!

But let’s go back to decoupling…

First, let me show you the exact circuit setup I’ve been using:


The green dotted line is the AWG signal generator, and it has an internal resistance of 50Ω. You can ignore the 1Ω resistor, it was intended to measure current through the cap, but it turns out that the 50Ω helps us get the same sort of information.

Imagine this circuit hooked up next to a digital chip, with high-frequency “noise” reaching the top of the cap. As you can see in yesterday’s plot, the 0.1 µF cap becomes more and more a conductor as the frequency increases – which is exactly what we want, because that means the remaining voltage will consist of just the remaining low frequency changes, which are more easily dealt with by the power supply source.

Another way to look at this circuit is as a low-pass RC filter. It lets the lower frequencies through, and shorts the higher frequencies to ground.

The plots so far have all been from 1 kHz to 1 MHz. Let’s now raise the frequency sweep range a bit – from 200 kHz to 20 MHz (just ignore the blue trace):


Now that is odd – the amplitude starts to rise again with frequencies nearing 20 MHz! In fact, there seems to be a “saddle point” roughly in the middle. This is about 2 Mhz (the scale is still logarithmic, so every 5 divisions is now a factor 10 with these sweeps).

What’s going on here?

The answer is that all electrical circuits and components have parasitic effects. In this case, the capacitor also has some inductance. An inductance (i.e. a coil which generates a magnetic field) is just the opposite of a capacitor: it’s impedance rises with frequency.

So this 0.1 µF cap is in fact not able to short out high frequencies at all – it leaves them unaffected. Note that with an ATmega running at 16 MHz, we’re very solidly in that range of frequencies where the decoupling cap is becoming less effective!

To give you an idea how odd these caps behave: let’s add a 0.01 µF capacitor in parallel. You’d expect the result to be equivalent to a 0.11 µF cap – with the saddle point simply moving to a different place on the plot, right? Not quite:


They each do their thing and have their effects super-imposed, generating a double saddle. That, by the way, is why the more demanding circuits use exactly this very same approach to decouple various frequencies at the same time – just put some different caps in parallel.

Tomorrow, I’ll take a few other familiar components through this sweep setup…

  1. While you’re at it: EMC-studies state that you should not only put these decoupling capacitors (yes, for every dedicated freq its own) as near as possible to the switching load, but also make sure that these caps are placed between source and target and not behind it with the current flowing somewhere else. But in 99% of all circuits these rules are negligible

  2. Thanks! That’s why parallel caps.

    So does anyone market multiple parallel caps in a single package? That seems like a good idea, but: mouser/digikey don’t seem to stock them; there’s probably a technical reason.

  3. @Doug – imagine a 0.1uF and 0.01uF in parallel between the Vcc and gnd. Each is acting independently of the other and we can approximate their behaviour by using for each an equivalent circuit of C, L, R in series. The L term comes mostly from the inductance standing in the way of getting the charge in and out of the active “plates”. That matches the trace shown of two characteristic curves, superimposed and effective.

    Combine both caps into the same package and they will share the same leads, roughly seeing the same L.

    Now the equivalent circuit is a single 1.1*C, L, R – back to the characteristic curve of a single device with the poor performance above the self-resonant frequency.

  4. Thanks martynj. But wouldn’t a single set of leads and the shorter wiring/traces to a single “multi-cap”(C)(TM)(SM)(Dibs!) have a lower total ESL compared to the multiple sets of leads and extra trace lengths to multiple caps? I don’t see the difference between sharing traces and sharing leads.

  5. @Doug – it is not the ESR (kind of a fairy tale ‘component’ ) but the inductance that is the issue. Part of the parasitic inductance is internal to a capacitor construction (current injected into where the lead joins the “plate” takes time to flow to all areas of the plate) and part comes from the more obvious device lead and trace to the ground plane/Vcc rail. By stacking multiple devices in the same package, they are forced to share part of the same L – to first order turning the device simply into C1+C2+C3 on legs. No improvement.

    Perhaps not seeing such a stacked device for sale might convince you – else get that Patent application in (alas, too late – even describing on a Weblog is considered ‘prior publication’)

    I am simplifying a complicated situation and to be fair, when faced with poor decoupling and limited board space, a quick fix can be much smaller C (and hence higher self resonant F) “piggy-back” or “turtle” style over the ineffective larger C.

    Now the challenge – how can I construct a decoupling capacitor with extra low parasitic L for just this task, decoupling Vcc to Ground on a PCB?

  6. Thanks again. Public domain is just fine with me.

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