The LPC812 does not come as Dual Inline Plastic (DIP) package, so it’s a bit more work to put it into service. But as before, all we need to program it, is a modified BUB with the RTS pin tied to the LPC’s ISP pin (PIO0_12). Here’s a breadboarded version:

Note that this uses a BUB configured to supply 3.3V on its VCC output pin, not 5V!

That’s 8 jumpers, including the two extra for the “+” and “-” rails on the left side of the breadboard. Note also the little orange 0.1 µF decoupling cap on that power rail.

The LPC812 is a superset of the LPC810, and wil run unmodified firmware as long as the same I/O pins are being used. This serial demo on GitHub only needs the serial TX pin, which is the same as on the LPC810 since it’s also used during ISP upload:

$ make
arm-none-eabi-g++ -mcpu=cortex-m0plus -mthumb -I../serial -Os -ggdb -fno-rtti -fno-exceptions   -c -o main.o main.cpp
[...]
lpc21isp -term -control -donotstart -bin firmware.bin /dev/tty.usbserial-AH01A0EG 115200 0
lpc21isp version 1.97
File firmware.bin:
loaded...
image size : 1584
[...]
Read part ID: LPC812M101FDH16, 16 kiB FLASH / 4 kiB SRAM (0x00008120)
[...]
Download Finished... taking 1 seconds
Terminal started (press Escape to abort)

DEV_ID = 00008120
GPREG0 = 00000000
GPREG1 = 00000000
GPREG2 = 00000000
GPREG3 = 00000000

This code is still compiled for a device with 4 KB flash and 1 KB RAM, but as you can see, it just works. To compile larger programs, the “LPC810.ld” setting in the Makefile needs to be changed to “LPC812.ld”, then the entire memory range will be available for code and data.

With this LPC812, we now have a setup with a lot more free I/O pins to play with.

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