Computing stuff tied to the physical world

Hooking up a dataflash chip

Flash memory has taken over the world, covering an amazing range of memory needs:

  • microcontrollers: kilobytes
  • dataflash chips: megabytes
  • USB- and (µ)SD cards: gigabytes
  • SSDs in laptops and servers: terabytes

They all maintain their contents for many years and can be erased and re-written tens of thousands of times. Long gone are the days of core memory and battery backed-up RAM.

Not only that, a tiny dataflash chip such as this one from Winbond costs less than €2:

8 SOIC sml

That gets you up to 16 megabytes of non-volatile storage, and the data is available faster than most most µCs can read them, with SPI clock rates up to 100 MHz. When connected in “Quad-SPI” mode, some µCs can in fact access 4 bits in parallel, giving a read-access rate of over 50 Mbyte per second. That’s random access: no rotational or seek delays in sight!

Writing is another matter. Usually, data can be written in units from 1 byte to one “page” (256 bytes, typically). Programming will normally take between 1 and 5 milliseconds – this is several orders of magnitude slowdown compared to the above sub-µs read timing.

It gets worse: you can’t just write anything anywhere – you can only turn a “1” bit into a “0” bit when programming any part of memory. After that, flash memory needs to be erased before re-programming it further. An erase cycle resets part or all of memory to 1’s.

The bad news? Erasure can only be done in sectors (or segments) of 4 Kb, usually (as well as a few larger units, all the way up to a full chip-erase).

The really bad news? Erasing a segment can often take some 100 ms, with a full chip erase sometimes requiring several minutes! – and after many erasures, these times will increase. During this time, the flash chip will be busy (though there are ways to suspend/resume it).

The exact specs differ somewhat between chip families and manufacturers.

But as with the RomVars implementation described earlier, we can use tricks to make this delay less important. The basic idea is to keep one or more “pre-erased” sectors available, and to start a new erasure when the amount of erased memory gets too low. This requires keeping track of what is in use, and “garbage collecting” sectors to remove unused gaps.

But first, let’s just hook up such an SPI dataflash chip, in this case the Winbond W25Q64 – a 64 Mbit chip, i.e. 8 MB. It can erase sectors of 4, 32, and 64 KB, as well as the entire chip.

It’s easier to do this with an LPC812 than an 8-DIP LPC810 with only 6 I/O pins: with the LPC810, 4 of these will be needed for SPI, making it hard to reserve the 4 I/O pins needed for uploading as well. Besides, the LPC812 (at least some models) supports two separate SPI peripherals – which makes it much simpler to interface to both dataflash and a radio:

DSC 5016

Note the use of a breakout board again, to allow using this SMD chip on a breadboard.

The pins (numbered in counter-clockwise order) are connected as follows:

  • pin 1: /cs    : PIO0_13
  • pin 2: dout   : PIO0_7
  • pin 3: /wprot : not connected
  • pin 4: gnd    : ground
  • pin 5: din    : PIO0_3
  • pin 6: clk    : PIO0_2
  • pin 7: /hold  : not connected
  • pin 8: vcc    : 3.3V

The write-protect and hold pins are not used, and have an internal pull-up.

Note that actual GPIO pin choices are fairly arbitrary, since we can connect them all up as needed through the LPC8xx’s switch matrix (except PIO0_10 and PIO0_11).

PIO0_2 and PIO0_3 are reserved for SWD hardware debugging on power-up, so the SWD functionality needs to be disabled to allow re-using them as ordinary I/O pins.

It’s probably good to point out here that most dataflash memory chips can only work with voltages up to 3.6V (and some not even that). These chips may not be connected to 5V!

Next, we’ll need some code to handle the SPI communication and verify that it all works.

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